As is known, artificial intelligence systems feature neural networks for performing complex tasks, in particular, for texture analysis, morphological kernel filtering in facsimile transmission, vehicle tracking systems, pattern recognition, hardware simulation in neural CAD systems, and preprocessing in optical character recognition applications.
Neural networks employ components known as neurons, similar to the biological elements of the same name and based on the addition and subtraction of appropriately weighted inputs, and for which various mathematical formalisms have been devised. Reference is made in the present invention to binary neurons according to the McCulloch-Pitts model, which stands out for the precision and elegance of its mathematical definition, and according to which, the output may assume only two binary values “0” and “1” and operates under a discrete time assumption, with predetermined neuron thresholds and weights. Each neuron comprises a processing element with a number of synaptic input connections and one output; and input and output signal flow is considered one-way.
In the classification phase neural network parameters are fixed and the neural network executes the recognition or the analysis starting from the information contained in the topology and in the weights of the neural network. FIG. 1 shows a symbolic representation of the McCulloch-Pitts model, in which x1, x2, . . . , xi are the inputs, w1, w2, . . . , wi the weights, and O the output. The neuron is represented by a node defining function f, which, when applied to the weighted inputs, supplies the output according to the equation:O=∫(Σwi*xi) 
Typically, the f function compares the sum of the weighted products of the inputs with a threshold, and, depending on the outcome of the comparison, determines the binary value of the output.
Various solutions are known for implementing neural networks, as described for example in S. Satyanarayana et al., “A Reconfigurable VLSI Neural Network,” IEEE Journal of Solid-State Circuits 27:1, January 1992; B. E. Boser et al., “An Analog Neural Network Processor with Programmable Topology,” IEEE Journal of Solid-State Circuits 26:12, December 1991; and A. Kramer et al., “EEPROM Device As a Reconfigurable Analog Element for Neural Networks,” IEDM, 1989, pp. 259-262.
All known solutions, however, involve a trade-off between power consumption and precision, require a large integration area, and are complex in design. Moreover, all known prior art solutions make it necessary to choose between solutions designed for high speed but requiring high power (current mode computation) and solutions designed for low power but operating at low speed (charge computation mode).
Analog implementations of Neural Network Architectures provide a framework for computation which is more efficient than standard digital techniques for certain problems. Typically, implementations of analog neural networks have been based on the use of either current or charge as the variable of computation.